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- Published at: 24 Feb, 2017
- Updated at: 06 Aug, 2023
Traditional bus VS High speed bus architecture
Traditional bus VS High speed bus architecture
Traditional Bus Architecture
A local bus connects the processor to the cache memory, which may support one or more local devices. A cache memory controller also connects this cache to this local bus and the system bus.
On the system, the bus is attached to the main memory modules. In this way, I/O transfers to and from the main memory across the system bus do not interfere with the processor’s activity. An expansion bus interface buffers data transfers between the bus and the I/O controllers on the expansion bus.
Some typical I/O devices that might be attached to the expansion bus include
Network cards (LAN)
SCSI (Small Computer System Interface)
Modem
Serial Com
Advantages of Traditional Bus Architecture
A separate cache structure insulates the processor from the requirement to access the main memory frequently.
This arrangement allows the system to support a wide variety of I/O devices and, at the same time, insulate memory to processor traffic from I/O traffic.
Disadvantages of Traditional Bus Architecture
The traditional bus architecture is reasonably efficient but begins to break down as higher, and higher performance is seen in the I/O devices.
High-Performance Bus Architecture
Similar to the previous arrangement, there is a local bus that connects the processor to a cache controller, which is, in turn, connected to a system bus that supports the main memory.
The cache controller is integrated into a bridge or buffering device that connects to a high-speed bus.
This (High Speed) bus supports connections to high-speed LANs, such as Fast Ethernet at 100 Mbps, video and graphics workstation controllers to local peripheral busses, including SCSI and Firewire.
An expansion bus still supports lower-speed devices, with an interface buffering traffic between the expansion bus and the high-speed bus.
Advantages of High-Performance Bus Architecture
The advantage of this arrangement is that the high-speed bus brings high-demand devices into closer integration with the processor and, at the same time, is independent of the processor.
So changes in processor architecture also do not affect the high-speed bus.
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